Smaller Magnetic Materials Push Boundaries of Nanotechnology

[vienna]

http://www.nytimes.com/2012/01/13/sc...echnology.html

IBM is like a sleeping giant who seems to have been forgotten in the gee-whiz of all the i-this and i-that world we live in, but every so often it wakes up and gives forth with some really astonishing new technology, not just a re-packaging of the already existing technology. The implications for things like solid state hard drives is amazing...

[nikimcbee]

Currently, antiferromagnetic materials are instrumental in two different types of data storage products. They are essential for the manufacture of the phonograph-needle-like recording heads used in today’s hard-disk drives. They are also used in a new type of memory chip known as spin-transfer-torque RAM, or STT-RAM, which is viewed by some as a future competitor for both DRAM and Flash memory chips.
Dr. Heinrich said that the tiny devices built with scanning tunneling microscopes would never be more than laboratory experiments. However, he noted that many research groups are exploring different ways of designing novel materials using self-assembly methods ranging from mechanical to biological approaches.
Industry executives said that as the semiconductor industry draws closer to exhausting the ability to scale down today’s circuits using lithographic tools that etch patterns on the surface of silicon wafers, an intense international hunt is under way for a manufacturing technology beyond microelectronics.

All I can say is "good luck with that." The big challenge is getting the litho and etch geometrys to work at that scale. Part 2 of the problem is being able to mass produce functioning chip with that small of an architechture. Sure, I bet they can make a few circuits that small, but to get them on one chip, working and debugging the problems is a whole other beast.

If you're interested, here some basic info:
http://en.wikipedia.org/wiki/Integrated_circuit

As of 2005, a fabrication facility (commonly known as a semiconductor fab) costs over $1 billion to construct,[19] because much of the operation is automated. Today, the most advanced processes employ the following techniques:

• The wafers are up to 300 mm in diameter (wider than a common dinner plate).
• Use of 32 nanometer or smaller chip manufacturing process. Intel, IBM, NEC, and AMD are using ~32 nanometers for their CPU chips. IBM and AMD introduced immersion lithography for their 45 nm processes[20]
• Copper interconnects where copper wiring replaces aluminium for interconnects.
• Low-K dielectric insulators.
• Silicon on insulator (SOI)
• Strained silicon in a process used by IBM known as strained silicon directly on insulator (SSDOI)
• Multigate devices such as tri-gate transistors being manufactured by Intel from 2011 in their 22 nm process.

Last I heard, AMD could bearly handly the 45 nm process (it was giving them a lot of problems, but I haven't kept up with them)

And the use of silicon to base chips on, may be a thing of the past in a matter of years.

[Betonov]

Originally Posted by nikimcbee

All I can say is "good luck with that." The big challenge is getting the litho and etch geometrys to work at that scale. Part 2 of the problem is being able to mass produce functioning chip with that small of an architechture. Sure, I bet they can make a few circuits that small, but to get them on one chip, working and debugging the problems is a whole other beast.

Don't worry, they're engineers

[nikimcbee]

Originally Posted by Betonov

Don't worry, they're engineers

God save us all then.

[nikimcbee]

If you work with one, you know what I'm talking about.

[Betonov]

Originally Posted by nikimcbee

If you work with one, you know what I'm talking about.

I work with 5
But our engineers are engineers on paper only, about as creative and able as a retarded ant