I think it depends a lot on how recent that article is, and what they're comparing. This is with DDR2, I think with DDR3 you'ld need to run it at 1600MHZ: DDR3 at 1600MHZ effectively runs at the same bus speed (400MHZ) as DDR2 at 800MHZ effectively.
All this stuff changes and evolves so fast it's really difficult to keep the facts straight.
* No, that's not right. Argh, I don't know.
All I know is that My FSB is at 400MHZ, external bus for CPU is 1600MHZ and CPU frequency is 3.2GHZ. DDR2 frequency is 800MHZ and all utilities report a ratio of 1:1 (synced).
**
http://icrontic.com/articles/core2_fsb_explained/2
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To provide an example: Intel boasts that their Core 2s with a 266MHz FSB actually have a “1066MHz FSB!” It’s not wrong, but it’s not totally truthful either. We have established that one megahertz is one million cycles, so a 266.66MHz FSB must have 266,660,000 cycles. If we were to double that frequency to derive the AGTL+ frequency, we would get 533.32MHz or 533,320,000 cycles. As the rise of the clock and fall of the clock can both perform a transfer, that means we must multiply the AGTL+ frequency by two (533.32m*2) to get our final number of transfers per second, which is 1,066,640,000T/s. If we divide that number by one million to get MT/s instead of T/s, we come to our final figure of 1066MT/s. Doesn’t that 1066 number look oddly familiar?
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In the days of SDRAM, a single clock cycle yielded a single transfer. Multiplying the speed of the RAM by the width of the bus indicated the amount of memory bandwidth available to the system. How were manufacturers going to reconcile the notion that their DDR, with two transfers per cycle, did double the workload of SDR at the same frequency? Their decision was obtuse but effective: If SDR did 133MT/s at 133MHz, and DDR did 266MT/s at 133MHz, then DDR should be advertised according to how many megahertz would be required of SDRAM to achieve the same result. The notion of doubling the actual frequency of the module to give it its “DDR Speed” was born. This antiquated idea has been carried forward to both DDR2 and DDR3.
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